In dynamic semiconductor memory storage devices it is essential that storage node capacitor cell plates be large enough to retain an adequate charge or capacitance in spite of parasitic capacitances and noise that may be present during circuit operation. As is the case for most semiconductor integrated circuitry, circuit density is continuing to increase at a fairly constant rate. The issue of maintaining storage node capacitance is particularly important as the density of DRAM arrays continues to increase for future generations of memory devices.
The ability to densely pack storage cells while maintaining required capacitance levels is a crucial requirement of semiconductor manufacturing technologies if future generations of expanded memory array devices are to be successfully manufactured.
One method of maintaining, as well as increasing, storage node size in densely packed memory devices is through the use of "stacked storage cell" design. With this technology, two or more layers of a conductive material such as polycrystalline silicon (polysilicon or poly) are deposited over an access device on a silicon wafer, with dielectric layers sandwiched between each poly layer. A cell constructed in this manner is known as a stacked capacitor cell (STC). Such a cell utilizes the space over the access device for capacitor plates, has a low soft error rate (SER) and may be used in conjunction with inter-plate insulative layers having a high dielectric constant.
However, it is difficult to obtain sufficient storage capacitance with a conventional STC capacitor as the storage electrode area is confined within the limits of its own cell area. Also, maintaining good dielectric breakdown characteristics between poly layers in the STC capacitor becomes a major concern once insulator thickness is appropriately scaled.
A paper submitted by N. Shinmura, et al., entitled "A Stacked Capacitor Cell with Ring Structure," Extended Abstracts of the 22nd International Conference on Solid State Devices and Materials, 1990, pp. 833-836, herein incorporated by reference, discusses a 3-dimensional stacked capacitor incorporating a ring structure around the main electrode to effectively double the capacitance of a conventional stacked capacitor.
The ring structure and its development is shown in FIGS. 1(c) through 1(g), pp. 834 of the article mentioned above. FIG. 1(a), on the same page shows a bird's eyeview of storage electrodes. The storage node is formed by two polysilicon layers that form a core electrode encircled by a ring structure. Capacitor dielectric film surrounds the whole surface of the storage node electrode and then is covered with a third polysilicon layer to form the top capacitor electrode and completes the storage cell. This design can be fabricated using current methods and increases storage capacitance by as much as 200%. However, the process flow needed to realize this ring capacitor structure requires precise alignment between two adjacent word lines and digits lines.
The present invention develops an existing stacked capacitor fabrication process without adding any photolithography step to construct a three-dimensional double ring stacked capacitor cell. The capacitor's bottom plate (or storage node plate) is centered over the buried contact (or node contact) connected to an access transistor's active area. The buried contact may be self-aligned depending on the process approach selected in the present invention. Additionally, the storage node does not need to be critically aligned on the node contact which allows the manufacture of a smaller cell area for a given lithographic resolution.